UCMODE=UCMODE_0, UCSSEL=UCSSEL_0, UCTR=UCTR_0, UCSYNC=UCSYNC_0, UCMM=UCMM_0, UCA10=UCA10_0, UCTXACK=UCTXACK_0, UCTXNACK=UCTXNACK_0, UCTXSTP=UCTXSTP_0, UCTXSTT=UCTXSTT_0, UCSWRST=UCSWRST_0, UCMST=UCMST_0, UCSLA10=UCSLA10_0
eUSCI_Bx Control Word Register 0
| UCSWRST | Software reset enable 0 (UCSWRST_0): Disabled. eUSCI_B reset released for operation 1 (UCSWRST_1): Enabled. eUSCI_B logic held in reset state |
| UCTXSTT | Transmit START condition in master mode 0 (UCTXSTT_0): Do not generate START condition 1 (UCTXSTT_1): Generate START condition |
| UCTXSTP | Transmit STOP condition in master mode 0 (UCTXSTP_0): No STOP generated 1 (UCTXSTP_1): Generate STOP |
| UCTXNACK | Transmit a NACK 0 (UCTXNACK_0): Acknowledge normally 1 (UCTXNACK_1): Generate NACK |
| UCTR | Transmitter/receiver 0 (UCTR_0): Receiver 1 (UCTR_1): Transmitter |
| UCTXACK | Transmit ACK condition in slave mode 0 (UCTXACK_0): Do not acknowledge the slave address 1 (UCTXACK_1): Acknowledge the slave address |
| UCSSEL | eUSCI_B clock source select 0 (UCSSEL_0): UCLKI 1 (UCSSEL_1): ACLK 2 (UCSSEL_2): SMCLK 3 (UCSSEL_3): SMCLK |
| UCSYNC | Synchronous mode enable 0 (UCSYNC_0): Asynchronous mode 1 (UCSYNC_1): Synchronous mode |
| UCMODE | eUSCI_B mode 0 (UCMODE_0): 3-pin SPI 1 (UCMODE_1): 4-pin SPI (master or slave enabled if STE = 1) 2 (UCMODE_2): 4-pin SPI (master or slave enabled if STE = 0) 3 (UCMODE_3): I2C mode |
| UCMST | Master mode select 0 (UCMST_0): Slave mode 1 (UCMST_1): Master mode |
| UCMM | Multi-master environment select 0 (UCMM_0): Single master environment. There is no other master in the system. The address compare unit is disabled. 1 (UCMM_1): Multi-master environment |
| UCSLA10 | Slave addressing mode select 0 (UCSLA10_0): Address slave with 7-bit address 1 (UCSLA10_1): Address slave with 10-bit address |
| UCA10 | Own addressing mode select 0 (UCA10_0): Own address is a 7-bit address 1 (UCA10_1): Own address is a 10-bit address |